The present invention relates to semiconductor processing and, more particularly, to a method of forming semiconductor devices and interconnects therebetween. A major objective of the present invention is to provide for interconnects without vias and with minimum spacing and overlap design rules.
The semiconductor industry has spurred technology by providing integrated circuits with greater functionality per unit area. In large part, miniaturization of integrated circuits is attributed to refinements in the lithographic systems which have permitted ever smaller feature sizes for the devices defined on an integrated circuit. For a given feature size, mask alignment tolerances and routing constraints limit the functional density of an integrated circuit.
The circuit density limits imposed by mask alignment tolerances can be described in connection with a conventional metal-oxide-silicon (MOS) transistor. A MOS transistor includes a source, a drain and a gate which can be used to control a current between the source and drain. Connecting such a transistor to other circuit devices on an integrated circuit requires that conductors be electrically connected to its source, drain and gate. Typically, the gate includes a metal or doped polysilicon (polycrystalline silicon) pedestal. The source and drain are formed in a silicon substrate to either side of this pedestal.
Conventionally, an insulating oxide is deposited over the source, drain and gate pedestal. Vias are formed through the oxide layer, for example, over the source and drain. A metal layer is deposited and patterned over the oxide. The metal layer accesses the source and drain through the vias to define conductive leads for the source and drain.
Care must be taken to ensure that the vias are properly aligned with the source and drain. Otherwise, they can cause a short with the gate or with the substrate to either side of the source and drain. This care is taken in the form of source and drain areas which are larger than otherwise necessary for device functioning. In other words, functional density is compromised by the tolerances required to ensure proper via alignment. Similar tolerances are required when connecting the metal interconnect material to other polysilicon conductors. Typically, the polysilicon conductors are enlarged where connections are to be made to prevent vias between the metal and polysilicon from shorting to the substrate.
Some tolerance requirements in the conventional interconnect approach are avoided by methods using a silicidable metal to define self-aligned source and drain contacts. A "silicidable metal" is a metal that can be sintered with an adjacent silicon material to form a metal silicide. A silicidable metal is deposited over the transistor without an intermediate insulating layer. Sintering causes the formation of silicide over the source and drain regions, as well as over the gate pedestal. A wet etch is used to remove the metal over regions where silicide has not formed.
Since the silicide is exposed at the source and drain, vias are not required over the source and drain to provide for electrical interconnection with subsequently formed interconnect metal. A more compact transistor is made possible since the transistor need not be oversized to accommodate the tolerances required for via formation over the source and drain. However, the source and drain are separated from the gate pedestal only by a thin oxide spacer, so some enlargement relative to the compact ideal for a given feature size is required to prevent source and drain interconnects from shorting to the gate.
The self-aligning approach can be extended to provide local interconnects by selectively reacting portions of the metal layer. The reacting can be done with nitrogen as disclosed by Thomas Tang, Che-Chia Wei, Roger Haken, Thomas Holloway, Chang-Feng Wan and Monte Douglas in "VLSI Local Interconnect Level Using Titanium Nitride", IEDM, 1985. Alternatively, silicide can be formed over the metal layer as disclosed by Devereaux C. Chen, Simon S. Wong, Paul Vande Voorde, P. Merchant, Tom R. Cass, Jun Amano, and Kuang-Yi Chiu in "A New Device Interconnect Scheme for Sub-Micron VLSI", IEDM, 1984. In either case, the reacting material is patterned over the metal using a mask. Therefore, strict masking tolerances are still required to ensure that interconnect metal does not short to the gate silicide.
A more serious disadvantage of the self-aligning approaches is that bridging interconnects are not provided conveniently. A bridging interconnect is one which crosses another interconnect without making an electrical connection thereto. Bridging interconnects are easily defined in conventional MOS processing in which the intermediate dielectric layer provides the required electrical insulation except where vias are formed. The self-aligning approaches do not form an dielectric layer through which vias are to be formed. While this provides for more compact devices, it makes insulated conductor crossings more difficult to obtain. In fact, the art cited above does not suggest how bridging interconnects can be made.
It is, therefore, a major objective of the present invention to provide a semiconductor process which provides for bridging interconnects without requiring vias to sources and drains. It is a further object of the invention to provide such a process which minimizes the need for mask alignment tolerances so that an integrated circuit structure with more compact transistor structures and interconnect routings can be provided.